1. Field of the Invention
The present invention relates to a method for controlling memory access, and more particularly to a method for controlling memory access through a cyclic redundancy check (CRC) for improving error check coverage.
2. Description of Related Art
In communication systems or computer systems, a cyclic redundancy check (CRC) can be adopted to improve error check coverage. The CRC is capable of monitoring if errors occur during data transmission after the data are transmitted or stored. In the process of transmitting the data, both the data receiver and the data source are required to implement a CRC computation, and one of the parties compares the CRC results respectively computed, so as to detect if the received data are erroneous.
Please refer to FIG. 1 which illustrates a conventional technology of applying a CRC-16 to memory access control in computer systems. The following description is given on the conditions of an 800-MHz system clock, an 8-bit data bus DQ<7:0>, and a 2-bit CRC bus CRC<1:0>. A 16-bit CRC result is acquired when the CRC-16 is applied.
As shown in FIG. 1, a main control circuit (e.g. CPU) issues reading instructions R-A and R-B to a memory. After several cycles, internal data D-A and D-B in the memory are retrieved in response to the reading instructions R-A and R-B. Here, the “internal data” denote that the data have not been placed on the data bus DQ<7:0>. The data D-A includes 8 bytes A0˜A7 while the data D-B includes 8 bytes B0˜B7. Based on the internal data D-A and D-B, a CRC computation CRC-AB is carried out by a memory controller.
When the data D-A and D-B are to be outputted by the memory, some bytes (e.g. A3 and B3) are placed on the CRC bus CRC<1:0> while the other bytes are placed on the data bus DQ<7:0>. Note that the space between A0 and A1 as indicated in FIG. 1 represents a non-transmission of data on the data bus DQ<7:0>.
As the data are outputted via the data bus DQ<7:0>, the CRC computation CRC-AB is initiated. As shown in FIG. 1, after the CRC computation CRC-AB is completed, the result of the CRC computation CRC-AB is transmitted via the CRC bus CRC<1:0>.
As such, the data D-A and D-B are read from the memory and the CRC result is outputted to the main control circuit.
However, the conventional technology has the following drawbacks of (1) complex hardware structure, large circuit layout, and high power consumption; (2) tight CAS to CAS delay latency (tCCD-L) e.g. 1.25 ns which leads to difficulty in design; (3) long time delay from issuing the reading instruction to outputting the data from the memory; (4) maintenance of data A and B in cache during the CRC computation, which leads to further difficulty in design; (5) difficulty in completion of the CRC computation within an extremely short time lapse (in 1.25 ns as exemplified by FIG. 1).
Accordingly, a method of controlling memory access is desirable given that the method is capable of overcoming said drawbacks of the conventional technology.